The present invention relates to the field of integrated circuit products, and more specifically to a buffer circuit that is tolerant to over-voltage. The invention also relates to a method for protecting buffer circuits from over-voltage.
Generally, gate-oxides in 0.35 .mu.m technology can withstand a maximum of 3.6 V Specifically, the potential difference between gate-to-source, gate-to-drain, and gate-to-substrate should not exceed 3.6 V If such potential differences exceed 3.6 V, electrical problems, such as current leakage, can occur. For example, a typical buffer circuit designed with CMOS digital integrated technology has driver PMOS transistors coupled in series between a supply-voltage VDD and an input/output node. Over-voltage can occur when a voltage at its input/output (I/O) node is higher than the I/O buffer supply-voltage VDD. For instance, when a 5 V input voltage appears at an I/O node, and VDD is 3.3 V (typical value), a driver PMOS transistor can turn on if the source-to-gate voltage is greater than the PMOS threshold voltage. Also, when a 5 V input voltage appears at the I/O node, a P+/N-well diode from the I/O node to an N-well underneath the PMOS transistors turns on. As a result, the diode is forward biased and current leaks from the I/O node to the N-well.
A need therefore remains for a simple and reliable buffer circuit that is tolerant to over-voltage, and for a reliable method for protecting buffer circuits from over-voltage. Such a circuit and method should thus prevent problems such as high leakage and gate-oxide damage. Also, such a circuit and method should be cost effective and require little space.